The present invention relates to solid-state imaging devices, manufacturing methods thereof, and electronic apparatuses such as cameras equipped with these solid-state imaging devices.
As a solid-state imaging device, an amplification-type solid-state imaging device typified by a MOS-type image sensor such as a CMOS (complementary metal oxide semiconductor)-type image sensor is well known. As another solid-state imaging sensor, a charge-transfer-type solid-state imaging device typified by a CCD (charge coupled device) image sensor is also well known. These solid-state imaging devices are widely used in digital cameras, digital video cameras, and the like. In recent years, MOS-type image sensors have been widely used as solid-state imaging devices installed in mobile devices such as camera cellular phones and PDAs (personal digital assistants) because of their low working voltages and low power consumption.
A MOS-type solid-state imaging device (hereinafter referred to as a MOS solid-state imaging device) is a device in that includes a plurality of pixels. Each pixel is composed of a photodiode, which functions as a photoelectric conversion element and at least one pixel transistor. The pixels are arranged in a two-dimensional array. Recently, in order to reduce the area occupied by the pixel transistors in each pixel to miniaturize the pixel, a so-called a component-shared-by-plural-pixels structure in which a single pixel transistor is shared by plural pixels has been proposed. In the component-shared-by-plural pixels structure, because a photodiode provided to each pixel can occupy a larger area, the sensitivity of the photodiode can be improved. For example, solid-state imaging devices with component-shared-by-two-pixels structures are disclosed in Japanese Unexamined Patent Application Publication Nos. 2004-172950, 2006-54276, and 2006-157953. In addition, solid-state imaging devices with component-shared-by-two-by-two-pixels structures are disclosed in Japanese Unexamined Patent Application Publication Nos. 2009-135319.
FIG. 23 is a diagram showing an example of a schematic configuration of a MOS solid-state imaging device with a component-shared-by-two-pixels structure. In this solid-state imaging device 101, photodiodes PD1 and PD2, which function as photoelectric conversion elements, are disposed in such a manner that they face each other with a floating diffusion element (FD) 102 disposed therebetween. A readout gate electrode 103 is formed between the photodiode PD1 and the floating diffusion element 102 through a gate insulating layer. A readout gate electrode 104 is also formed between the photodiode PD2 and the floating diffusion element 102 through a gate insulating layer. A transistor Tr11 is composed of the readout gate electrodes 103 and the floating diffusion element 102, and a transistor Tr12 is composed of the gate electrode 104, and the floating diffusion element 102. The transistors Tr11 and Tr12 are respectively connected to the photodiodes PD1 and PD2. One sharing unit is defined as a combination of these two pixels including the photodiodes PD1 and PD2, and plural sharing units are arranged in a two-dimensional array. A reset transistor Tr2, an amplifying transistor Tr3, and a selection transistor Tr3 are prepared for each sharing unit.
The reset transistor Tr2 is composed of a pair of source/drain regions 105 and 106, and a reset gate electrode 109. The amplifying transistor Tr3 is composed of a pair of source/drain regions 106 and 107, and an amplifying gate electrode 110. The selection transistor Tr4 is composed of a pair of source/drain regions 107 and 108, and a selection gate electrode 111. These readout transistors Tr11 and Tr12, the reset transistor Tr2, the amplifying transistor Tr3, and the selection transistor Tr4 are so-called pixel transistors.
Although not shown in FIG. 23, the floating diffusion element 102 is connected to the amplifying gate electrode 110 and one source/drain region 105 of the reset transistor Tr2. The other source/drain region 106 is connected to a power supply VDD. In addition, one source/drain region 108 of the selection transistor Tr4 is connected to a vertical signal line,
On the other hand, a back-illuminated type solid-state imaging device having a light-receiving surface on the back side of a substrate that is opposite to the surface of the substrate on which multilayer interconnections, pixel transistors, and the like are formed, is disclosed in Japanese Unexamined Patent Application Publication Nos. 2003-31785.